LESSON READING // 05
RESOURCE ISOLATION
When online inference shares a GPU with batch work, establish a hardware boundary first, then balance latency and throughput with bounded batching and asynchronous feeding.
Write down answers as you go; the estimate includes code tracing and practice.
PLAY THE INTERACTIVE LESSON→- 01ORIENT + OBJECTIVES05 MIN
- 02MENTAL MODEL08 MIN
- 03DEEP DIVES15 MIN
- 04CODE TRACE12 MIN
- 05HISTORY + ECOSYSTEM08 MIN
- 06PRACTICE + REVIEW12 MIN
Extend profiling from kernels to end-to-end pipelines and locate queueing, contention, and movement bottlenecks.
The game separates streams, MIG, and batching; the lab judges resource policy through tail latency, not average throughput alone.
- Lesson 02
- Basic service-latency concepts
- P50/P95/P99 distinction
- Nsight Systems
- Triton Model Analyzer (optional)
- MIG-capable GPU (optional)
ORIENT + OBJECTIVES
REMEMBER THIS FIRST
Concurrency expresses independence, isolation creates boundaries, and scheduling controls queues inside those boundaries.
BY THE END, YOU SHOULD BE ABLE TO
- 01
Separate concurrency, priority, resource isolation, and service scheduling.
- 02
Explain which compute and memory paths MIG GPU instances isolate.
- 03
Design maximum batch, queue window, and double buffering from a latency budget.
- 04
Choose observability signals for a shared-GPU experiment.
BUILD THE MENTAL MODEL
- 01CONTEND
Two streams submit independently but still share SMs, cache, and memory bandwidth.
- 02ISOLATE
MIG creates GPU instances from supported profiles, bounding compute and memory paths.
- 03FEED
Inside an instance, bound batch size and wait time, then use buffers to reduce copy/compute bubbles.
CONCEPT DEEP DIVES
A STREAM IS NOT QOS
Stream priority is a scheduling hint, not a hard reservation of SMs, L2, or memory bandwidth.
MIG USES DISCRETE PROFILES
GPU instances come from hardware-supported combinations, not arbitrary percentage sliders.
ISOLATION STILL LEAVES A QUEUE
Dynamic batching trades among maximum batch, queue delay, request priority, and latency objectives.
INDEPENDENT SUBMISSION DOES NOT CREATE A RESOURCE BOUNDARY
CUDA streams give workloads independent command flows, yet kernels still compete for SMs, registers, L2, and memory bandwidth. Stream priority can influence pending work, but it does not reserve a fixed share or necessarily preempt a running large kernel.
Start with the objective: security separation, fault containment, or predictable interference? Different goals may call for processes, MPS, time slicing, MIG, or separate GPUs. One mechanism's guarantee cannot be projected onto every layer.
PAUSE AND REASONCan a high-priority stream guarantee completion within 5 ms?+
REFERENCE ANSWERNo. Priority is a scheduling hint; running kernels, contention, queueing, and model time still govern latency.
MIG MAKES PROFILE-BASED INSTANCE BOUNDARIES
On supported GPUs, MIG combines compute and memory slices into GPU instances. Each instance receives isolated address and memory-system paths, reducing interference from another instance's cache or bandwidth behavior and defining clearer QoS and fault boundaries.
Profiles are discrete hardware-supported combinations. Each smaller instance has less capacity and compute, so model fit and overload must be revalidated. MIG also does not replace container, identity, or application authorization controls.
PAUSE AND REASONCan MIG split a GPU into arbitrary 37% and 63% instances?+
REFERENCE ANSWERNo. Configurations must use supported, layout-compatible profiles.
BATCHING SPENDS LATENCY BUDGET TO BUY THROUGHPUT
Dynamic batching shares one execution across requests and can improve matrix shapes, but the first request waits for the batch to form. Maximum queue delay directly consumes end-to-end latency budget; derive it from the target P95/P99 rather than maximizing batch size.
Double buffering overlaps input movement for one slot with compute in another, but cannot remove model compute. Highly variable request shapes may need separate queues, ragged batching, or priority policy to prevent one request from dragging the batch.
PAUSE AND REASONWhy is a larger maximum batch not always better?+
REFERENCE ANSWERIt may increase throughput but also queue time, memory use, and one-batch execution time, worsening tail latency.
PUT IT BACK INTO CODE
01while (serving) {02 batch = queue.take(max_batch, max_queue_delay);03 copy_async(slot[next], batch);04 infer_async(slot[current]);05 swap(current, next);06}TRACE THE CODE
- 01BUDGETDEFINE max_queue_delay FIRST
Queue time is one piece of end-to-end latency; leave budget for network, preprocessing, execution, and response.
- 02FORMDISPATCH ON SIZE OR TIME
A batch leaves when maximum size or oldest-request wait is reached.
- 03BUFFERSEPARATE COPY AND EXECUTION SLOTS
One slot receives input while the other executes; completion must precede reuse.
- 04MEASURETRACK THROUGHPUT AND TAILS
Average latency hides queue spikes. Observe queue, copy, compute, and P95/P99 by request class.
KNOWLEDGE ATLAS
OPTIONAL REFERENCE · REVISIT AS NEEDED · OUTSIDE THE CORE 60 MINUTES
CORE VOCABULARY
- Throughput
- Requests or samples completed per unit time; it does not reveal how long one request waited.
- Tail Latency
- High-percentile latency such as P95/P99, exposing slow requests and contention.
- Queue Delay
- Time waiting for a batch, stream, memory, or execution resource.
- Dynamic Batching
- Combining requests within a bounded waiting window to improve GPU utilization.
- MIG
- Hardware partitioning, introduced with Ampere, that assigns isolated compute and memory-system resources to instances.
WORKED EXAMPLE
- 01NORMAL LOAD
L = λW = 80 × 0.10 = 8, so eight requests are in flight on average.
- 02CONTENTION
If W rises to 0.25 s at the same arrival rate, L = 80 × 0.25 = 20.
- 03INTERPRET IT
Twelve additional requests now wait or execute, increasing queue and memory pressure.
DIAGNOSTIC PLAYBOOK
Mean latency is fine; P99 explodes
- INSPECT FIRST
- Long batches, head-of-line blocking, background jobs, reclamation, and bursts
- EVIDENCE
- Per-request queue/copy/compute spans and the latency distribution
Throughput drops after enabling MIG
- INSPECT FIRST
- Whether the profile fits the working set and whether one job needs full-GPU resources
- EVIDENCE
- Per-instance utilization, memory, bandwidth, and QoS under identical traffic
A larger batch does not raise utilization
- INSPECT FIRST
- Pre/post-processing, movement, shape variation, memory, and CPU supply
- EVIDENCE
- An end-to-end timeline and stage queue lengths—not one GPU percentage
HARDWARE → ECOSYSTEM
- 01SINGLE-JOB OWNERSHIP
Batch jobs optimized full-GPU throughput.
Utilization was simple, but online multi-tenancy was weak. - 02STREAM / MPS SHARING
Multiple workflows submitted concurrently.
Utilization rose alongside cache, bandwidth, and tail interference. - 03MIG + SERVICE ORCHESTRATION
Hardware isolation joined batching, scheduling, monitoring, and containers.
The problem moved from kernels to QoS and capacity planning.
HARDWARE + ECOSYSTEM COORDINATE
MIG introduced hardware-supported GPU instances on Ampere data-center GPUs, giving clients isolated compute and memory paths. Service software such as Triton made batching, queue policy, and model placement system-design concerns.
PRACTICE + REVIEW
Can two CUDA streams guarantee that a large batch will not interfere with an online request?
- A. Yes, each stream reserves half the SMs
- B. No, they can still compete for one resource pool
- C. Yes, if host priority is raised
REVEAL ANSWER+
Streams enable potential concurrency but do not establish hard resource boundaries. Isolation and queue scheduling live at different layers.
Do separate processes, streams, and MIG instances provide the same isolation?
HINT+
Compare address space, scheduling, and hardware resources.
REFERENCE ANSWER+
No. Processes separate software address spaces, streams order commands, and MIG allocates isolated compute/memory paths. Platform details still matter.
P99 target is 50 ms: network/preprocess 8, model 30, response 4. What queue budget remains?
HINT+
Subtract, then reserve jitter margin.
REFERENCE ANSWER+
A static 8 ms remains, but max_queue_delay should be below 8 ms to leave margin and must be load-tested.
Double buffering overwrites slot[next] while the prior batch still uses it. Fix it.
HINT+
Each slot needs a completion signal.
REFERENCE ANSWER+
Associate an event/future with each slot and wait for that slot's copy and compute before reuse.
How would you test whether MIG stabilizes online latency?
HINT+
Build shared versus isolated controls.
REFERENCE ANSWER+
Hold model, traffic, and background batch load constant; compare P50/P95/P99, throughput, errors, memory, and bandwidth while recording profiles and intra-instance scheduling.
OPTIONAL HANDS-ON LAB
OUTSIDE THE CORE 60 MINUTES · REQUIRES A SUITABLE CUDA / GPU ENVIRONMENT
LAB GOAL
EVALUATE SHARED GPU + BOUNDED BATCHING WITH TAIL LATENCY
Compare shared resources, bounded microbatching, and MIG when available under fixed traffic.PROCEDURE
- 01
Generate repeatable online requests and background batch load.
- 02
Capture shared-GPU throughput, P50/P95/P99, and a timeline.
- 03
Add max_batch, max_queue_delay, and double buffering under identical traffic.
- 04
Repeat with an explicit MIG profile only when supported.
Submit throughput/tail-latency results, a timeline, and a statement separating isolation from scheduling.
Use separate long- and short-request queues to study head-of-line blocking and fairness.